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PCA8565
Real time clock/calendar
Rev. 02 -- 16 June 2009 Product data sheet
1. General description
The PCA8565 is a CMOS1 real time clock and calendar optimized for low power consumption. A programmable clock output, interrupt output and voltage-low detector are also provided. All address and data are transferred serially via a two-line bidirectional I2C-bus. Maximum bus speed is 400 kbit/s. The built-in word address register is incremented automatically after each written or read data byte. AEC-Q100 compliant (PCA8565TS) for automotive applications.
2. Features
I Provides year, month, day, weekday, hours, minutes and seconds based on a 32.768 kHz quartz crystal I Century flag I Clock operating voltage: 1.8 V to 5.5 V I Extended operating temperature range: -40 C to +125 C I Low backup current; typical 0.65 A at VDD = 3.0 V and Tamb = 25 C I 400 kHz two-wire I2C-bus interface (at VDD = 1.8 V to 5.5 V) I Programmable clock output for peripheral devices (32.768 kHz, 1.024 kHz, 32 Hz and 1 Hz) I Alarm and timer functions I Internal power-on reset I I2C-bus slave address: read A3h and write A2h I Open-drain interrupt pin I One integrated oscillator capacitor
3. Applications
I Automotive I Industrial I Other applications that require a wide operating temperature range
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 16.
NXP Semiconductors
PCA8565
Real time clock/calendar
4. Ordering information
Table 1. Ordering information Package Name PCA8565TS PCA8565BS TSSOP8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm Version SOT505-1 SOT650-1 Type number
HVSON10 plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 3 x 3 x 0.85 mm
5. Marking
Table 2. Marking codes Marking code 8565 8565S Type number PCA8565TS PCA8565BS
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6. Block diagram
OSCI OSCILLATOR 32.768 kHz OSCO MONITOR 00h 01h 0Dh POWER-ON RESET TIME 02h 03h VDD VSS 04h 05h 06h 07h WATCH DOG 08h Seconds Minutes Hours Days Weekdays Months_century Years CONTROL Control_1 Control_2 CLKOUT_control DIVIDER CLOCK OUT CLKOUT
ALARM FUNCTION 09h 0Ah SDA SCL I2C INTERFACE 0Bh 0Ch Minute_alarm Hour_alarm Day_alarm Weekday_alarm INTERRUPT TIMER FUNCTION INT
PCA8565
0Eh 0Fh
Timer_control Timer
001aah661
Fig 1.
Block diagram of PCA8565
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7. Pinning information
7.1 Pinning
terminal 1 index area OSCI OSCO n.c. OSCI OSCO INT VSS 1 2 3 4
001aaj754
1 2 3 4 5
10 n.c. 9 VDD CLKOUT SCL SDA
PCA8565BS
8 7 6
8 7
VDD CLKOUT SCL SDA
INT VSS
PCA8565TS
6 5
001aaj753
Transparent top view
Top view. For mechanical details see Figure 28.
For mechanical details see Figure 29.
Fig 2.
Pin configuration of PCA8565TS (TSSOP8)
Fig 3.
Pin configuration of PCA8565BS (HVSON10)
7.2 Pin description
Table 3. Symbol OSCI OSCO n.c. INT VSS SDA SCL CLKOUT VDD
[1]
Pin description Pin TSSOP8 1 2 3 4 5 6 7 8 HVSON10 1 2 3, 10 4 5[1] 6 7 8 9 oscillator input oscillator output do not connect and do not use as feed through; connect to VDD if floating pins are not allowed interrupt output (open-drain; active LOW) ground serial data I/O serial clock input clock output, open-drain positive supply voltage Description
The die paddle (exposed pad) is wired to VSS but should not be electrically connected.
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8. Device protection diagram
OSCI
VDD
OSCO
CLKOUT
INT
SCL
VSS
SDA
PCA8565
mce169
Fig 4.
Device diode protection diagram of PCA8565
9. Functional description
The PCA8565 contains sixteen 8-bit registers with an auto-incrementing address register, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the Real Time Clock (RTC), a programmable clock output, a timer, an alarm, a voltage-low detector and a 400 kHz I2C-bus interface. All 16 registers are designed as addressable 8-bit registers although not all bits are implemented:
* The first two registers (memory address 00h and 01h) are used as control and status
registers
* The registers at memory addresses 02h through 08h are used as counters for the
clock function (seconds up to years counters)
* Address locations 09h through 0Ch contain alarm registers which define the
conditions for an alarm
* The register at address 0Dh controls the CLKOUT output frequency * At address 0Eh is the timer control register and address 0Fh contains the timer value
The arrays SECONDS, MINUTES, HOURS, DAYS, WEEKDAYS, MONTHS, YEARS as well as the bit fields MINUTE_ALARM, HOUR_ALARM, DAY_ALARM and WEEKDAY_ALARM are all coded in Binary Coded Decimal (BCD) format. When one of the RTC registers is read the contents of all time counters are frozen. This prevents faulty reading of the clock or calendar during a carry condition (see Section 10.5.3).
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9.1 Register overview
Table 4. Register overview and control bits default values Bit positions labeled as - are not implemented. Bit positions labeled as N should always be written with logic 0. Reset values are shown in Table 7. Address Register name Bit 7 Control registers 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Control_1 Control_2 Seconds Minutes Hours Days Weekdays Months_century Years Minute_alarm Hour_alarm Day_alarm Weekday_alarm CLKOUT_control Timer_control Timer TEST1 N VL C N N STOP N N TI_TP TESTC AF N TF N AIE N TIE 6 5 4 3 2 1 0
Time and date registers SECONDS (0 to 59) MINUTES (0 to 59) HOURS (0 to 23) DAYS (1 to 31) WEEKDAYS (0 to 6) MONTHS (1 to 12)
YEARS (0 to 99) AE_M AE_H AE_D AE_W FE TE MINUTE_ALARM (0 to 59) HOUR_ALARM (0 to 23) DAY_ALARM (1 to 31) WEEKDAY_ALARM (0 to 6) FD TD
Alarm registers
CLKOUT control register Timer registers COUNTDOWN_TIMER
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Real time clock/calendar
9.2 Control registers
9.2.1 Register Control_1
Table 5. Bit 7 6 5 Register Control_1 (address 00h) bits description Value 0[1] 1 N STOP 0[2] 0[1] 1 Description normal mode EXT_CLK test mode default value RTC source clock runs all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC clock is stopped (CLKOUT at 32.768 kHz is still available) 4 3 N TESTC 0[2] 0 1[1] 2 to 0 N
[1] [2] Default value. Bits labeled as N should always be written with logic 0.
Symbol TEST1
default value power-on reset override facility is disabled; set to logic 0 for normal operation power-on reset override may be enabled default value
000[2]
9.2.2 Register Control_2
Table 6. Bit 4 7 to 5 N TI_TP Register Control_2 (address 01h) bits description Value 000[1] 0[2] 1 Description default value INT is active when TF is active (subject to the status of TIE) INT pulses active according to Table 26 (subject to the status of TIE); Remark: note that if AF and AIE are active then INT will be permanently active 3 2 1 0 AF TF AIE TIE 0[2] 1 0[2] 1 0[2] 1 0[2] 1
[1] [2]
Symbol
alarm flag inactive alarm flag active timer flag inactive timer flag active alarm interrupt disabled alarm interrupt enabled timer interrupt disabled timer interrupt enabled
Bits labeled as N should always be written with logic 0. Default value.
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9.3 Reset
The PCA8565 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the I2C-bus logic is initialized including the address pointer. All other registers are set according to Table 7.
Table 7. Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh
[1]
Register reset values[1] Register name Control_1 Control_2 Seconds Minutes Hours Days Weekdays Months_century Years Minute_alarm Hour_alarm Day_alarm Weekday_alarm CLKOUT_control Timer_control Timer Bit 7 0 x 1 1 x x x x x 1 1 1 1 1 0 x 6 0 x x x x x x x x x x x x x x x 5 0 0 x x x x x x x x x x x x x x 4 0 0 x x x x x x x x x x x x x x 3 1 0 x x x x x x x x x x x x x x 2 0 0 x x x x x x x x x x x x x x 1 0 0 x x x x x x x x x x x 0 1 x 0 0 0 x x x x x x x x x x x 0 1 x
Registers labeled `x' are undefined at power-on and unchanged by subsequent resets.
9.4 Time and date registers
The majority of the registers are coded in the BCD format to simplify application use.
Table 8. Bit 7 VL Register Seconds (address 02h) bits description Value 0 1[1] 6 to 4 SECONDS 0 to 3 to 0
[1] [2] Start-up value. Values shown in decimal.
Symbol
Place value Description clock integrity is guaranteed integrity of the clock information is not guaranteed actual seconds coded in BCD format
5[2] 9[2]
ten's place unit place
0 to
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Seconds coded in BCD format Upper-digit (ten's place) Bit 6 0 0 0 0 0 1 1 Bit 5 0 0 0 0 0 0 0 Bit 4 0 0 0 0 1 1 1 Digit (unit place) Bit 3 0 0 0 1 0 1 1 Bit 2 0 0 0 0 0 0 0 Bit 1 0 0 1 0 0 0 0 Bit 0 0 1 0 1 0 0 1
Table 9.
Seconds value in decimal 00 01 02 : 09 10 : 58 59 Table 10. Bit 7 3 to 0
[1]
Register Minutes (address 03h) bits description Value 0 to 5[1] 0 to 9[1] Place value Description ten's place unit place unused actual minutes coded in BCD format
Symbol -
6 to 4 MINUTES
Values shown in decimal.
Table 11. Bit 7 to 6 -
Register Hours (address 04h) bits description Value 0 to 2[1] 0 to 9[1] Place value Description ten's place unit place unused actual hours coded in BCD format
Symbol
5 to 4 HOURS 3 to 0
[1]
Values shown in decimal.
Table 12. Bit 5 to 4 3 to 0
[1] [2]
Register Days (address 05h) bits description Value 0 to 0 to 3[2] 9[2] Place value Description ten's place unit place unused actual day coded in BCD format
Symbol DAYS[1]
7 to 6 -
The PCA8565 compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00. Values shown in decimal.
Table 13. Bit 7 to 3 -
Register Weekdays (address 06h) bits description Value 0 to 6[1] Description unused actual weekday values, see Table 14
Symbol
2 to 0 WEEKDAYS
[1] Values shown in decimal.
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Weekday assignments Bit 2 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1
Table 14. Day[1] Sunday Monday Tuesday
Wednesday Thursday Friday Saturday
[1]
Definition may be re-assigned by the user.
Table 15. Bit 7 C[1]
Register Months_century (address 07h) bits description Value 0[2] 1 0 to 1[3] 0 to 9[3] Place value Description ten's place unit place indicates the century is x indicates the century is x + 1 unused actual month coded in BCD format, see Table 16
Symbol
6 to 5 4 3 to 0
[1] [2] [3]
MONTHS
This bit may be re-assigned by the user. This bit is toggled when the years register overflows from 99 to 00. Values shown in decimal.
Table 16. Month
Month assignments coded in BCD format Upper-digit (ten's place) Bit 4 0 0 0 0 0 0 0 0 0 1 1 1 Digit (unit place) Bit 3 0 0 0 0 0 0 0 1 1 0 0 0 Bit 2 0 0 0 1 1 1 1 0 0 0 0 0 Bit 1 0 1 1 0 0 1 1 0 0 0 0 1 Bit 0 1 0 1 0 1 0 1 0 1 0 1 0
January February March April May June July August September October November December
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Register Years (08h) bits description Value 0 to 0 to 9[1] 9[1] Place value Description ten's place unit place actual year coded in BCD format
Table 17. Bit 3 to 0
[1]
Symbol
7 to 4 YEARS
Values shown in decimal.
9.5 Data flow
Figure 5 shows the data flow and data dependencies starting from the 1 Hz clock tick.
1 Hz tick
SECONDS
MINUTES
HOURS
LEAP YEAR CALCULATION
DAYS
WEEKDAY
MONTHS
YEARS
C
013aaa092
Fig 5.
Data flow for the time function
If the time registers are written or read by making individual access to the chip, then there is the risk that the time will increment between accesses. This has to be avoided by stopping the increment of the time circuit. After access is completed, the time circuit is allowed to continue running and any request to increment that occurred during the access is initiated. As a consequence of this method, it is important to read or write all time registers in one access i.e. seconds up to years. Failing to comply with this method could result in the time becoming corrupted. As an example, if the time (seconds through to hours) are set in one access and then in a second access the date is set, it is possible that the time may increment between the two accesses. A similar problem exists when reading. A roll over may occur between reads thus giving the minutes from one moment and the hours from the next. Recommended method for reading the time: 1. Send a START condition and the slave address for write (A2h). 2. Set the address pointer to registers Seconds (02h).
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3. Send a RESTART condition or STOP followed by START. 4. Send the slave address for read (A3h). 5. Read the register Seconds. 6. Read the register Minutes. 7. Read the register Hours. 8. Read the register Days. 9. Read the register Weekdays. 10. Read the register Months_century. 11. Read the register Years. 12. Send a STOP condition.
9.6 Alarm function
When one or more of the alarm registers are loaded with a valid minute, hour, day or weekday and its corresponding bit alarm enable (AE_x) is logic 0, then that information is compared with the actual minute, hour, day and weekday.
check now signal AE_M MINUTE ALARM = MINUTE TIME
example AE_M= 1 1 0 AE_H
HOUR ALARM = HOUR TIME set alarm flag, AF(1) AE_D DAY ALARM = DAY TIME
AE_W WEEKDAY ALARM = WEEKDAY TIME
013aaa088
(1) Only when all enabled alarm settings are matching. It's only on increment to a matched case that the alarm is set, see Section 9.6.2.
Fig 6.
Alarm function block diagram
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9.6.1 Alarm registers
Table 18. Bit 7 Register Minute_alarm (address 09h) bits description Value 0 1[1] 6 to 4 MINUTE_ALARM 3 to 0
[1] [2] Default value. Values shown in decimal.
Symbol AE_M
Place value Description ten's place unit place minute alarm is enabled minute alarm is disabled minute alarm information coded in BCD format
0 to 5[2] 0 to 9[2]
Table 19. Bit 7 6 3 to 0
[1] [2]
Register Hour_alarm (address 0Ah) bits description Value 0 1[1] 0 to 2[2] 0 to 9[2] Place value Description ten's place unit place hour alarm is enabled hour alarm is disabled unused hour alarm information coded in BCD format
Symbol AE_H -
5 to 4 HOUR_ALARM
Default value. Values shown in decimal.
Table 20. Bit 7 6 3 to 0
[1] [2]
Register Day_alarm (address 0Bh) bits description Value 0 1[1] 0 to 0 to 3[2] 9[2] Place value Description ten's place unit place day alarm is enabled day alarm is disabled unused day alarm information coded in BCD format
Symbol AE_D -
5 to 4 DAY_ALARM
Default value. Values shown in decimal.
Table 21. Bit 7
Register Weekday_alarm (address 0Ch) bits description Value 0 1[1] 6[2] Description weekday alarm is enabled weekday alarm is disabled unused weekday alarm information coded in BCD format
Symbol AE_W
6 to 3 -
2 to 0 WEEKDAY_ALARM 0 to
[1] [2] Default value. Values shown in decimal.
9.6.2 Alarm flag
When all enabled comparisons first match, the Alarm Flag (AF) is set. AF will remain set until cleared using the interface. Once AF has been cleared it is only set again when the time increments to match the alarm condition once more.
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Alarm registers which have their bit AE_x at logic 1 are ignored. Table 23 shows an example for clearing bit AF but leaving bit TF unaffected. Clearing the flags is made by a write command; therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior.
minutes counter
44
45
46
minute alarm
45
AF
INT when AIE = 1
001aaf903
Example where only the minute alarm is used and no other interrupts are enabled.
Fig 7.
AF timing
To prevent the timer flags being overwritten while clearing AF, a logical AND is performed during a write access. Writing a logic 1 will cause the flag to maintain its value, whereas writing a logic 0 will cause the flag to be reset.
Table 22. Register Control_2 Flag location in register Control_2 Bit 7 6 5 4 3 AF 2 TF 1 0 -
The following table shows what instruction must be sent to clear bit AF. In this example bit TF is unaffected.
Table 23. Register Control_2 Example to clear only AF (bit 3) in register Control_2 Bit 7 6 5 4 3 0 2 1 1 0 -
9.7 Timer functions
The 8-bit countdown timer at address 0Fh is controlled by the timer control register at address 0Eh. The timer control register determines one of 4 source clock frequencies for the timer (4.096 kHz, 64 Hz, 1 Hz, or 160 Hz) and enables or disables the timer. The timer counts down from a software-loaded 8-bit binary value. At the end of every countdown, the timer sets the timer flag (TF). The TF is cleared using the interface. The asserted TF is used to generate an interrupt (INT). The interrupt is generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of TF. Bit TI_TP is used to control this mode selection. When reading the timer, the actual countdown value is returned.
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9.7.1 Register Timer_control
Table 24. Bit 7 TE Register Timer_control (address 0Eh) bits description Value 0[1] 1 6 to 2 1 to 0 TD[1:0] 00 01 10 11[2]
[1] [2] Default value. These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to 1 Hz for power saving. 60
Symbol
Description timer is disabled timer is enabled unused timer source clock frequency select[2] 4.096 kHz 64 Hz 1 Hz
1 60
-
Hz
The timer register is an 8-bit binary countdown timer. It is enabled and disabled via the bit TE in register Timer_control. The source clock for the timer is also selected by the TD[1:0] in register Timer_control. Other timer properties such as interrupt generation are controlled via register Control_2. For accurate read back of the countdown value, the I2C-bus clock (SCL) must operate at a frequency of at least twice the selected timer clock. Since it is not possible to freeze the countdown timer counter during read back, it is recommended to read the register twice and check for consistent results.
Table 25. Bit 7 to 0 Timer (address 0Fh) bits description Value Description n CountdownPeriod = -------------------------------------------------------------SourceClockFrequency
Symbol
COUNTDOWN_TIMER 00h to FFh countdown value = n;
9.8 Interrupt output
9.8.1 Bits TF and AF
When an alarm occurs, AF is set to 1. Similarly, at the end of a timer countdown, TF is set to 1. These bits maintain their value until overwritten using the interface. If both timer and alarm interrupts are required in the application, the source of the interrupt is determined by reading these bits. To prevent one flag being overwritten while clearing another a logic AND is performed during a write access.
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TE
TI_TP TF: TIMER SET CLEAR PULSE GENERATOR 2 TRIGGER CLEAR from interface: clear TF AF: ALARM FLAG SET CLEAR from interface: clear AF
013aaa087
to interface: read TF 0 1
TIE
E.G.AIE 0 1
COUNTDOWN COUNTER
INT
to interface: read AF
AIE
set alarm flag, AF
When bits TIE and AIE are disabled, pin INT will remain high-impedance.
Fig 8.
Interrupt scheme
9.8.2 Bits TIE and AIE
These bits activate or deactivate the generation of an interrupt when TF or AF is asserted respectively. The interrupt is the logical OR of these two conditions when both AIE and TIE are set.
9.8.3 Countdown timer interrupts
The pulse generator for the countdown timer interrupt uses an internal clock and is dependent on the selected source clock for the countdown timer and on the countdown value n. As a consequence, the width of the interrupt pulse varies (see Table 26).
Table 26. INT operation (bit TI_TP = 1) INT period (s) n = 1[1] 4096 64 1
1 60 1 1 1 1 8192 128 64 64
Source clock (Hz)
n>1
1 4096 1 64 1 64 1 64
[1]
n = loaded countdown value. Timer stopped when n = 0.
9.9 Clock output
A programmable square wave is available at pin CLKOUT. Operation is controlled by the CLKOUT_control register at address 0Dh. Frequencies of 32.768 kHz (default), 1.024 kHz, 32 Hz and 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes high-impedance.
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Register CLKOUT_control (address 0Dh) bits description Value 0 1[1] Description the CLKOUT output is inhibited and CLKOUT output is set to high-impedance the CLKOUT output is activated unused frequency output at pin CLKOUT 00[1] 01 10 11 32.768 kHz 1.024 kHz 32 Hz 1 Hz
Table 27. Bit 7 FE
Symbol
6 to 2 1 to 0 FD[1:0]
-
[1]
Default value.
9.10 Voltage-low detector
The PCA8565 has an on-chip voltage-low detector. When VDD drops below Vlow, bit VL in the Seconds register is set to indicate that the integrity of the clock information is no longer guaranteed. The VL flag is cleared using the interface. Bit VL is intended to detect the situation when VDD is decreasing slowly, for example under battery operation. Should VDD reach Vlow before power is re-asserted then bit VL is set. This indicates that the time may be corrupt (see Figure 9).
mgr887
VDD normal power operation period of battery operation
Vlow t
VL set
Fig 9.
Voltage-low detection
9.11 External clock (EXT_CLK) test mode
A test mode is available which allows for on-board testing. In such a mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit TEST1 in register Control_1. Then pin CLKOUT becomes an input. The test mode replaces the internal 64 Hz signal with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then generate an increment of one second.
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The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is divided down to 1 Hz by a 26 divide chain called a pre-scaler. The pre-scaler can be set into a known state by using bit STOP. When bit STOP is set, the pre-scaler is reset to 0 (STOP must be cleared before the pre-scaler can operate again). From a STOP condition, the first 1 second increment will take place after 32 positive edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment. Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the pre-scaler can be made. Operation example: 1. Set EXT_CLK test mode (Control_1, bit TEST1 = 1). 2. Set STOP (Control_1, bit STOP = 1). 3. Clear STOP (Control_1, bit STOP = 0). 4. Set time registers to desired value. 5. Apply 32 clock pulses to CLKOUT. 6. Read time registers to see the first change. 7. Apply 64 clock pulses to CLKOUT. 8. Read time registers to see the second change. Repeat 7 and 8 for additional increments.
9.12 STOP bit function
The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP bit function will cause the upper part of the prescaler (F2 to F14) to be held in reset and thus no 1 Hz ticks will be generated (see Figure 10). The time circuits can then be set and will not increment until the STOP bit is released (see Figure 11 and Table 28).
OSC STOP DETECTOR 32768 Hz 16384 Hz 8192 Hz
reset
4096 Hz
F0
F1
F2 RES
F13 RES
2 Hz
F14 1 Hz tick RES stop
OSC
1 Hz 32 Hz 1024 Hz 32768 Hz
013aaa089
CLKOUT source
Fig 10. STOP bit
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The STOP bit function will not affect the output of 32.768 kHz but will stop 1.024 kHz, 32 Hz and 1 Hz. The lower two stages of the prescaler (F0 and F1) are not reset and because the I2C-bus is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between zero and one 8.192 kHz cycle (see Figure 11).
8192 Hz
stop released 0 s to 122 s
001aaf912
Fig 11. STOP bit release timing Table 28. Bit STOP 0 1 1 0 First increment of time circuits after STOP bit release Prescaler bits F0F1-F2 to F14 01-0 0001 1101 0100
[1]
1 Hz tick
Time hh:mm:ss 12:45:12 12:45:12 08:00:00 08:00:00
Comment
Clock is running normally prescaler counting normally prescaler is reset; time circuits are frozen prescaler is reset; time circuits are frozen prescaler is now running : 0 to 1 transition of F14 increments the time circuits : 0 to 1 transition of F14 increments the time circuits STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally XX-0 0000 0000 0000 New time is set by user XX-0 0000 0000 0000 STOP bit is released by user XX-0 0000 0000 0000
0.507813- 0.507935 s
XX-1 0000 0000 0000 XX-0 1000 0000 0000 XX-1 1000 0000 0000 : 11-1 1111 1111 1110 00-0 0000 0000 0001 10-0 0000 0000 0001
08:00:00 08:00:00 08:00:00 : 08:00:00 08:00:01 08:00:01 : 08:00:01 08:00:01 08:00:01 : 08:00:01 08:00:02
013aaa076
11-1 1111 1111 1111 00-0 0000 0000 0000 10-0 0000 0000 0000 : 11-1 1111 1111 1110 00-0 0000 0000 0001
[1]
F0 is clocked at 32.768 kHz.
PCA8565_2
1.000000 s
:
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The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset (see Table 28) and the unknown state of the 32 kHz clock.
9.13 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device. The setting of this mode requires that the I2C-bus pins, SDA and SCL, be toggled in a specific order as shown in Figure 12. All timings are required minimums. Once the override mode has been entered, the device immediately stops being reset and normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus access. The override mode may be cleared by writing a logic 0 to TESTC. TESTC must be set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0 during normal operation has no effect except to prevent entry into the POR override mode.
500 ns SDA
2000 ns
SCL 8 ms power up override active
mgm664
Fig 12. POR override sequence
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10. Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
10.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 13).
SDA
SCL data line stable; data valid change of data allowed
mbc621
Fig 13. Bit transfer
10.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P), see Figure 14.
SDA
SDA
SCL S START condition P STOP condition
SCL
mbc622
Fig 14. Definition of START and STOP conditions
10.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Figure 15).
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SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER / RECEIVER
mba605
SLAVE RECEIVER
MASTER TRANSMITTER
Fig 15. System configuration
10.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement
mbc602
1
2
8
9
Fig 16. Acknowledgement on the I2C-bus
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10.5 I2C-bus protocol
10.5.1 Addressing
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The PCA8565 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. The PCA8565 slave address is shown in Figure 17.
1
0
1
0
0
0
1
R/W
group 1
group 2
mce189
Fig 17. Slave address
10.5.2 Clock and calendar read/write cycles
The I2C-bus configuration for the different PCA8565 read and write cycles is shown in Figure 18, Figure 19 and Figure 20. The word address is a 4-bit value that defines which register is to be accessed next. The upper four bits of the word address are not used.
acknowledgement from slave
acknowledgement from slave
acknowledgement from slave
S
SLAVE ADDRESS
0A
WORD ADDRESS
A
DATA
A
P
R/W
n bytes auto increment memory word address
mbd822
Fig 18. Master transmits to slave receiver (write mode)
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acknowledgement from slave
acknowledgement from slave
acknowledgement from slave
acknowledgement from master
S
SLAVE ADDRESS
0A
WORD ADDRESS
A
S
SLAVE ADDRESS
1A
DATA
A
R/W
at this moment master transmitter becomes master receiver and PCA8565 slave receiver becomes slave transmitter
R/W
n bytes auto increment memory word address
no acknowledgement from master
DATA
1
P
last byte auto increment memory word address
001aaj743
Fig 19. Master reads after setting word address (write word address; read data)
acknowledgement from slave
acknowledgement from master
no acknowledgement from master
S
SLAVE ADDRESS
1A
DATA
A
DATA
1
P
R/W
n bytes auto increment word address
last byte auto increment word address
mgl665
Fig 20. Master reads slave immediately after first byte (read mode)
10.5.3 Interface watchdog timer
During read/write operations, the time counting circuits are frozen. To prevent a situation where the accessing device becomes locked and does not clear the interface, the PCA8565 has a built in watchdog timer. Should the interface be active for more than 1 s from the time a valid slave address is transmitted, then the PCA8565 will automatically clear the interface and allow the time counting circuits to continue counting. Under a correct data transfer, the watchdog timer is stopped on receipt of a START or STOP condition. The watchdog is implemented to prevent the excessive loss of time due to interface access failure e.g. if main power is removed from a battery backed-up system during an interface access. Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The watchdog will trigger between 1 s and 2 s after receiving a valid slave address.
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tW < 1 s WD timer data time counters valid slave address WD timer running data data data
running
time counters frozen
running
013aaa090
a. Correct data transfer: read or write
1 s < tW < 2 s WD timer data time counters valid slave address running data WD timer running data data data transfer fail WD trips
time counters frozen
running
013aaa091
b. Incorrect data transfer: read or write Fig 21. Interface watchdog timer
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11. Limiting values
Table 29. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD ISS IDD VI II IO Ptot Tamb Tstg VESD Ilu
[1] [2] [3] [4]
Parameter supply voltage ground supply current supply current input voltage input current output current total power dissipation ambient temperature storage temperature electrostatic discharge voltage latch-up current
Conditions
Min -0.5 -50 -50 -0.5 -10 -10 -40
[1]
Max +6.5 +50 -50 +6.5 +10 +10 300 +125 +150 3000 1100 250
Unit V mA mA V mA mA mW C C V V mA
-65 -
HBM CDM
[2] [3] [4]
According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be stored at a temperature of +5 C to +45 C and a humidity of 25 % to 75 %. Pass level; Human Body Model (HBM) according to JESD22-A114. Pass level; Charged-Device Model (CDM), according to JESD22-C101. Pass level; latch-up testing, according to JESD78.
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12. Characteristics
12.1 Static characteristics
Table 30. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +125 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise specified. Symbol Supplies VDD Vlow IDD supply voltage for clock data integrity low voltage supply current for low voltage detection interface active fSCL = 400 kHz fSCL = 100 kHz interface inactive (fSCL = 0 Hz); Tamb = 25 C CLKOUT disabled VDD = 5.0 V VDD = 4.0 V VDD = 3.0 V VDD = 2.0 V VDD = 5.0 V; Tamb = 125 C CLKOUT enabled at 32 kHz VDD = 5.0 V VDD = 4.0 V VDD = 3.0 V VDD = 2.0 V VDD = 5.0 V;Tamb = 125 C Inputs VIL VIH ILI Ci Outputs IOL LOW-level output current VOL = 0.4 V; VDD = 5 V on pin SDA on pin INT VO = VDD or VSS; on pin CLKOUT ILO
[1] [2] [3]
[2] [2] [1] [1]
Parameter
Conditions
Min 1.8 Vlow -
Typ 0.9 -
Max 5.5 5.5 1.7 820 220
Unit V V V A A
-
750 700 650 600 750 1000 900 800 700 1000
1500 1400 1300 1200 5000 2000 1800 1600 1400 6000 0.3VDD 5.5 +1 7
nA nA nA nA nA nA nA nA nA nA V V A pF
LOW-level input voltage HIGH-level input voltage input leakage current input capacitance on pins SCL and SDA on pin OSCI on pins SCL and SDA; VI = VDD or VSS
[3]
VSS - 0.3 0.7VDD 0.7VDD -1 0 -
VDD + 0.3 V
-3 -1 -1 -1
0
+1
mA mA mA A
output leakage current
Timer source clock = 160 Hz, level of pins SCL and SDA is VDD or VSS. Worst case is at high temperature and high supply voltage. Tested on sample basis.
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1.5 IDD (A) 1.0
mld970
1.5 IDD (A) 1.0
mld971
0.5
0.5
0 0 2 4 VDD (V) 6
0 0 2 4 VDD (V) 6
Tamb = 25 C; Timer = 1 minute; CLKOUT disabled.
Tamb = 25 C; Timer = 1 minute; CLKOUT = 32 kHz.
Fig 22. IDD as a function of VDD
1.5 IDD (A) 1.0
mld972
Fig 23. IDD as a function of VDD
mld973
4 frequency deviation (ppm) 2
0
0.5
-2
-4 0 -40 0 40 80 120 T (C) 160 0 2 4 6
VDD (V)
VDD = 3 V; Timer = 1 minute; CLKOUT = 32 kHz.
Tamb = 25 C; normalized to VDD = 3 V.
Fig 24. IDD as a function of temperature
Fig 25. Frequency deviation as a function of VDD
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12.2 Dynamic characteristics
Table 31. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +125 C; fosc = 32.768 kHz; quartz Rs = 40 k; CL = 8 pF; unless otherwise specified. Symbol Oscillator CL(itg) fosc/fosc integrated load capacitance relative oscillator frequency variation VDD = 200 mV; Tamb = 25 C
[1]
Parameter
Conditions
Min 15 -
Typ 25 2x 10-7
Max 35 -
Unit pF ppm
Quartz crystal parameters (f = 32.768 kHz) Rs CL Ctrim CLKOUT I2C-bus fSCL tHD;STA tSU;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tBUF tSU;STO tSP Cb
[1] [2] [3] [4] [5]
series resistance load capacitance trimmer capacitance duty cycle on pin CLKOUT timing characteristics SCL clock frequency hold time (repeated) START condition set-up time for a repeated START condition LOW period of the SCL clock HIGH period of the SCL clock rise time of both SDA and SCL signals fall time of both SDA and SCL signals data set-up time data hold time bus free time between a STOP and START condition set-up time for STOP condition pulse width of spikes that must be suppressed by the input filter capacitive load for each bus line
[2] [3][4] [5]
5 0.6 0.6 1.3 0.6 100 0 4.7 0.6 -
10 50 ( C OSCI C OSCO ) ( C OSCI + C OSCO )
40 25 400 0.3 0.3 50 400
k pF pF % kHz s s s s s s ns ns s s ns pF
CLKOUT output
Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series. C L ( itg ) = -------------------------------------------For fCLKOUT = 1.024 kHz, 32 Hz and 1 Hz. All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD. A detailed description of the I2C-bus specification is given in the document UM10204. I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
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SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA tSU;STO
mga728
Fig 26. I2C-bus timing waveforms
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13. Application information
VDD
SDA MASTER TRANSMITTER/ RECEIVER
1 F
SCL
VDD SCL CLOCK CALENDAR OSCI OSCO
PCA8565
SDA VSS VDD
R
R
R: pull-up resistor tr R= Cb
SDA SCL (I2C-bus)
mce168
Fig 27. Application diagram of PCA8565
13.1 Quartz frequency adjustment
13.1.1 Method 1: fixed OSCI capacitor
By evaluating the average capacitance necessary for the application layout, a fixed capacitor can be used. The frequency is best measured via the 32.768 kHz signal available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average f f = 5 x 10 -6 ). Average deviations of 5 minutes per year can be easily achieved.
13.1.2 Method 2: OSCI trimmer
Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a trimmer is possible.
13.1.3 Method 3: OSCO output
Direct measurement of OSCO out (allowing for test probe capacitance).
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14. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
D
E
A
X
c y HE vMA
Z
8
5
A2 pin 1 index
A1
(A3)
A
Lp L
1
e bp
4
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 6 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18
Fig 28. Package outline SOT505-1 (TSSOP8) of PCA8565TS
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HVSON10: plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 3 x 3 x 0.85 mm
SOT650-1
0
1 scale
2 mm
X D B A
A E A1 c detail X
terminal 1 index area
terminal 1 index area 1 L
e1 e b 5 vMCAB wMC y1 C
C y
Eh
10 Dh DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D(1) 3.1 2.9 Dh 2.55 2.15 E(1) 3.1 2.9
6
Eh 1.75 1.45
e 0.5
e1 2
L 0.55 0.30
v 0.1
w 0.05
y 0.05
y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT650-1 REFERENCES IEC --JEDEC MO-229 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-01-22 02-02-08
Fig 29. Package outline of SOT650-1 (HVSON10) of PCA8565BS
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15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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15.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 30) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 32 and 33
Table 32. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 33. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 30.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 30. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
16. Abbreviations
Table 34. Acronym BCD CDM CMOS HBM I2C IC MSB MSL PCB POR RC RTC SMD Abbreviations Description Binary Coded Decimal Charged-Device Model Complementary Metal Oxide Semiconductor Human Body Model Inter-Integrated Circuit Integrated Circuit Most Significant Bit Moisture Sensitivity Level Printed-Circuit Board Power-On Reset Resistance and Capacitance Real Time Clock Surface Mount Device
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17. Revision history
Table 35. Revision history Release date 20090616 Data sheet status Product data sheet Change notice Supersedes PCA8565_1 Document ID PCA8565_2 Modifications
* * * * * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors Legal texts have been adapted to the new company name where appropriate Added HVSON10 package Added ESD and latch-up values Changed values in limiting values table from relative to absolute values Combined IDD1 to IDD3 values to one IDD value description with different conditions Added automotive compliant statement To gain a better understanding of the device - many parts of the data sheet have been rewritten - many new drawings have been added
PCA8565_1
20030331
Product data
-
-
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18. Legal information
18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
18.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA8565_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 16 June 2009
38 of 39
NXP Semiconductors
PCA8565
Real time clock/calendar
20. Contents
1 2 3 4 5 6 7 7.1 7.2 8 9 9.1 9.2 9.2.1 9.2.2 9.3 9.4 9.5 9.6 9.6.1 9.6.2 9.7 9.7.1 9.8 9.8.1 9.8.2 9.8.3 9.9 9.10 9.11 9.12 9.13 10 10.1 10.2 10.3 10.4 10.5 10.5.1 10.5.2 10.5.3 11 12 12.1 12.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Device protection diagram . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Register overview . . . . . . . . . . . . . . . . . . . . . . . 6 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 7 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 7 Register Control_2 . . . . . . . . . . . . . . . . . . . . . . 7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Time and date registers . . . . . . . . . . . . . . . . . . 8 Data flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 12 Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 13 Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Timer functions . . . . . . . . . . . . . . . . . . . . . . . . 14 Register Timer_control . . . . . . . . . . . . . . . . . . 15 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 15 Bits TF and AF . . . . . . . . . . . . . . . . . . . . . . . . 15 Bits TIE and AIE . . . . . . . . . . . . . . . . . . . . . . . 16 Countdown timer interrupts. . . . . . . . . . . . . . . 16 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Voltage-low detector . . . . . . . . . . . . . . . . . . . . 17 External clock (EXT_CLK) test mode . . . . . . . 17 STOP bit function . . . . . . . . . . . . . . . . . . . . . . 18 Power-On Reset (POR) override . . . . . . . . . . 20 Characteristics of the I2C-bus. . . . . . . . . . . . . 21 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 START and STOP conditions . . . . . . . . . . . . . 21 System configuration . . . . . . . . . . . . . . . . . . . 21 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Clock and calendar read/write cycles . . . . . . . 23 Interface watchdog timer. . . . . . . . . . . . . . . . . 24 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 27 Static characteristics. . . . . . . . . . . . . . . . . . . . 27 Dynamic characteristics . . . . . . . . . . . . . . . . . 29 13 13.1 13.1.1 13.1.2 13.1.3 14 15 15.1 15.2 15.3 15.4 16 17 18 18.1 18.2 18.3 18.4 19 20 Application information . . . . . . . . . . . . . . . . . Quartz frequency adjustment . . . . . . . . . . . . . Method 1: fixed OSCI capacitor . . . . . . . . . . . Method 2: OSCI trimmer . . . . . . . . . . . . . . . . Method 3: OSCO output. . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 31 31 31 31 32 34 34 34 34 35 36 37 38 38 38 38 38 38 39
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 June 2009 Document identifier: PCA8565_2

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